1. Field of the Invention
The present invention relates to clock signal generating circuits and more particularly, to a clock signal generating circuit which can be suitably made in the form of a semiconductor integrated circuit and can operate with a small-amplitude signal having a high frequency. The present invention also relates to a phase comparator and variable delay circuit which are used in the clock signal generating circuit.
2. Description of the Related Art
As a microprocessor or a semiconductor integrated circuit (LSI) including a semiconductor memory and so on is required to operate with a higher frequency, a system clock for synchronization between LSI chips or an internal clock for synchronization between circuits within the respective LSI chips has been increasingly required in recent years to have a higher frequency.
In order to synchronize an external clock as a system clock supplied from an external LSI chip with an internal clock for the internal circuits of the LSI chip, a phase locked loop (PLL) circuit is employed. The PLL circuit functions to control a frequency of an oscillator on the basis of a difference in phase between two frequencies. The operation of a prior art PLL circuit will be briefly explained referring to a block diagram of FIG. 1.
The illustrated PLL circuit includes an input circuit 1 for receiving an external clock signal Clkin, a phase comparator 10 for comparing the external clock signal with an internal clock signal with respect to their phase, a loop filter 8 for filtering a phase difference comparison voltage signal received from the phase comparator 10 to generate a control voltage signal, and a voltage controlled oscillator (which will be referred to merely as the VCO, hereinafter) 9 for controlling a frequency on the basis of the control voltage signal received from the loop filter 8. An internal clock signal generated by the voltage controlled oscillator 9 is applied to the phase comparator 10 as a signal PLL1.
In this case, the external clock signal Clkin received from an external clock signal input terminal 5 is first amplified by the input circuit 1 into a signal usable in the PLL circuit. The phase comparator 10 compares the amplified signal with the internal clock signal generated at the VCO 9 with respect to their phase and sends its comparison result to the VCO 9 via the loop filter 8.
In the phase comparison of the signals Clkin and PLL1, if the signal Clkin is lagging the signal PLL1 with respect to phase, then the value of the control voltage signal generated by the loop filter 8 is increased to increase the frequency of the output signal of the VCO 9. If the signal PLL1 is leading the signal Clkin, then the frequency of the output signal of the VCO 9 is controllably decreased so as not to produce a phase shift between the signals Clkin and PLL1.
Further, a delay locked loop (DLL) circuit is used to synchronize the signal Clkin with a rising edge of the next clock delayed by one cycle. The DLL circuit, which operates in a manner similar to that of the PLL circuit, is provided with a delay line for delaying the input signal by just one cycle. That is, the DLL circuit is to provide a delay corresponding to one cycle of the synchronizing operation, and its allowable frequency range is limited.
In this way, the LSI chip is designed to correct the phase difference between the external and internal clocks with use of the PLL or DLL circuit to transmit an accurate signal. Meanwhile, as the operational frequency of the LSI is increased in these years, the amplitude of the signal has been decreased. Accordingly, when it is desired to use an external signal in an internal circuit, it becomes necessary for the input circuit 1 to perform its amplifying operation, which causes a processing delay in the input circuit 1. Further, even a signal passing through a wiring line connected from an input terminal to the input circuit will be delayed.
Furthermore, the operational speed of the LSI chip is influenced by the chip surrounding environment so that, for example, temperature or voltage value will cause the oscillation frequency of an oscillator to vary or the operation of the input circuit to be delayed.